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128mx64 bits unbuffered ddr so-dimm this document is a general product descript ion and is subject to change without notic e. hynix semiconductor does not assume any responsibility for use of circuits descr ibed. no patent licenses are implied. rev. 0.2 / apr. 2004 1 hymd512m646b(l)f8-d43/d4 document title 128mx64 bits unbuffered ddr so-dimm revision history no. history draft date remark 0.1 initial draft jan. 2004 0.2 1) reflected a ?notational? change in module thickness on page 14 - not real ! - 2) corrected some typos apr. 2004
128mx64 bits unbuffered ddr so-dimm this document is a general product descript ion and is subject to change without notic e. hynix semiconductor does not assume any responsibility for use of circuits descr ibed. no patent licenses are implied. rev. 0.2 / apr. 2004 2 hymd512m646b(l)f8-d43/d4 description hynix hymd512m646b(l)f8-d43/d4 series is unbuffered 2 00-pin double data rate synchronous dram small outline dual in-line memory modules (so-dimms) which are or ganized as 128mx64 high-speed memory arrays. hynix hymd512m646b(l)f8-d43/d4 series consists of sixteen 64mx8 ddr sdram in fbga packages on a 200pin glass- epoxy substrate. hynix hymd512m646b(l )f8-d43/d4 series provide a high performance 8-byte interface in 67.60mmx 31.75mm form factor of in dustry standard. it is suitable for easy interchange and addition. hynix hymd512m646b(l)f8-d43/d4 series is designed for high speed of up to 200mhz and offers fully synchronous operations referenced to both rising and falling edges of diff erential clock inputs. while all addresses and control inputs are latched on the rising edges of the clock, data, data st robes and write data masks inputs are sampled on both ris- ing and falling edges of it. the data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. high speed frequencies, programmable latencies and burst lengths allow variety of device operation in hi gh performance memory system. hynix hymd512m646b(l)f8-d43/d4 series incorporates spd(s erial presence detect). seri al presence detect func- tion is implemented via a serial 2,048- bit eeprom. the first 128 by tes of serial pd data are programmed by hynix to identify dimm type, capacity and other the information of di mm and the last 128 bytes are available to the customer. features ordering information part no. power supply clock frequency interface form factor hymd512m646b(l)f8-d43 v dd =2.6v v ddq =2.6v 200mhz (ddr400 3-3-3) sstl_2 200pin unbuffered so-dimm 67.6mm x 31.75mm x 1mm hymd512m646b(l)f8-d4 200mhz (ddr400 3-4-4) ? 1gb (128m x 64) unbuffered ddr so-dimm based on 64mx8 ddr sdram ? 200-pin small outline dual in-line memory module (so-dimm) ? 2.6v +/- 0.1v vdd and vddq power supply ? all inputs and outputs are compatible with sstl_2 interface ? fully differential clock operations (ck & /ck) with 200mhz ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? data(dq), data strobes and write masks latched on both rising and falling edges of the clock ? data inputs on dqs center s when write (centered dq) ? data strobes synchronized with output data for read and input data for write ? programmable cas latency 3 supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? tras lock-out function supported ? internal four bank operatio ns with single pulsed ras ? auto refresh and self refresh supported ? 8192 refresh cycles / 64ms * jedec defined specifications compliant
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 3 pin description pin assignment pin pin description pin pin description ck0, /ck0, ck1, /ck1 differential clock inputs vddq dqs power supply cs0, cs1 chip select input vss ground cke0, cke1 clock enable input vref reference power supply /ras, /cas, /we commend sets inputs vddspd power supply for spd a0 ~ a1 2 address sa0~sa2 e 2 prom address inputs ba0, ba1 bank address scl e 2 prom clock dq0~dq63 data inputs/outputs sda e 2 prom data i/o dqs0~dqs7 data strobe inputs/outputs vddid vdd identification flag dm0~dm7 data-in mask du do not use vdd power supply nc no connection pin name pin name pin name pin name pin name pin name pin name pin name 1 vref 2 vref 51 vss 52 vss 101 a9 102 a8 151 dq42 152 dq46 3 vss 4 vss 53 dq19 54 dq23 103 vss 104 vss 153 dq43 154 dq47 5 dq0 6 dq4 55 dq24 56 dq28 105 a7 106 a6 155 vdd 156 vdd 7 dq1 8 dq5 57 vdd 58 vdd 107 a5 108 a4 157 vdd 158 /ck1 9 vdd 10 vdd 59 dq25 60 dq29 109 a3 110 a2 159 vss 160 ck1 11 dqs0 12 dm0 61 dqs3 62 dm3 111 a1 112 a0 161 vss 162 vss 13 dq2 14 dq6 63 vss 64 vss 113 vdd 114 vdd 163 dq48 164 dq52 15 vss 16 vss 65 dq26 66 dq30 115 a10/ap 116 ba1 165 dq49 166 dq53 17 dq3 18 dq7 67 dq27 68 dq31 117 ba0 118 /ras 167 vdd 168 vdd 19 dq8 20 dq12 69 vdd 70 vdd 119 /we 120 /cas 169 dqs6 170 dm6 21 vdd 22 vdd 71 nc 72 nc 121 /cs0 122 /cs1 171 dq50 172 dq54 23 dq9 24 dq13 73 nc 74 nc 123 nc 124 du 173 vss 174 vss 25 dqs1 26 dm1 75 vss 76 vss 125 vss 126 vss 175 dq51 176 dq55 27 vss 28 vss 77 nc 78 nc 127 dq32 128 dq36 177 dq56 178 dq60 29 dq10 30 dq14 79 nc 80 nc 129 dq33 130 dq37 179 vdd 180 vdd 31 dq11 32 dq15 81 vdd 82 vdd 131 vdd 132 vdd 181 dq57 182 dq61 33 vdd 34 vdd 83 nc 84 nc 133 dqs4 134 dm4 183 dqs7 184 dm7 35 ck0 36 vdd 85 du 86 du 135 dq34 136 dq38 185 vss 186 vss 37 /ck0 38 vss 87 vss 88 vss 137 vss 138 vss 187 dq58 188 dq62 39 vss 40 vss 89 nc 90 vss 139 dq35 140 dq39 189 dq59 190 dq63 41 dq16 42 dq20 91 nc 92 vdd 141 dq40 142 dq44 191 vdd 192 vdd 43 dq17 44 dq21 93 vdd 94 vdd 143 vdd 144 vdd 193 sda 194 sa0 45 vdd 46 vdd 95 cke1 96 cke0 145 dq41 146 dq45 195 scl 196 sa1 47 dqs2 48 dm2 97 nc 98 du 147 dqs5 148 dm5 197 vddspd 198 sa2 49 dq18 50 dq22 99 a12 100 a11 149 vss 150 vss 199 vddid 200 du
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 4 functional block diagram dm /cs dqs d8 dm /cs dqs d9 dm /cs dqs dm /cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 /cs dqs d0 dq10 dq11 dq12 dq13 dq14 dq15 dm /cs dqs d1 dm /cs dqs d2 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm /cs dqs dq32 dq33 dq35 dq36 dq37 dq38 dq39 dm /cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm /cs dqs d5 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dm /cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm /cs dqs d7 dm0 dqs0 dm4 dqs4 dq8 dq9 dm1 dqs1 dm2 dqs2 dm3 dqs3 dm7 dqs7 dm6 dqs6 dm5 dqs5 /cs0 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dm /cs dqs d13 dm /cs dqs d15 dm /cs dqs d10 /cs1 d11 d3 d14 d6 d4 d12 dm /cs dqs i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 d12 dq34 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 dm wp scl sda a0 a1 a2 sa0 sa1 sa2 serial pd strap:see note 4 vdd spd vdd /vddq vref vss vddid spd do-d15 do-d15 do-d15 ba0-ba1 a0-a12 /ras /cas cke0 /we ba0-ba1 : sdrams d0-d15 a0-a12 : sdrams d0-d15 /ras : sdrams d0-d15 /cas : sdrams d0-d15 cke : sdrams d0-d7 /we : sdrams d0-d15 cke1 cke : sdrams d8-d15 4. vddid strap connections (for memory device vdd, vddq) : strap out (open) : vdd = vddq strap in (vss) : vdd vddq note : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors : 22 ohms 5%.
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 5 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta= 0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with < 5ns of duration. 3. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on vref may not exceed +/- 2% of the dc value. ac operating conditions (ta= 0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference between the input level on ck and the input on /ck. 2. the value of v ix is expected to equal 0.5*v ddq of the trans mitting device and must track vari ations in the dc level of the same. parameter symbol rating unit operating temperature (ambient) t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 1.0 x # of components w soldering temperature t time t solder 260 / 10 o c / sec parameter symbol min typ. max unit note power supply voltage v dd 2.5 2.6 2.7 v power supply voltage v ddq 2.5 2.6 2.7 v 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 0.49*vddq 0.5*vddq 0.51*vddq v3 parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) v ref - 0.31 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 6 ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t )50 ? series resistor (r s )25 ? output load capacitance for access time measurement (c l )30 pf
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 7 v ref v tt r t =50 ? zo=50 ? c l =30pf output capacitance (t a =25 o c, f=100mhz ) note : 1. vdd = min. to max., vddq = 2.3v to 2.7v, vodc = vddq/2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by desi gn and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input capacitance a0 ~ a13, ba0, ba1 c in1 50 68 pf input capacitance /ras, /cas, /we c in2 50 68 pf input capacitance cke0, cke1 c in3 36 48 pf input capacitance /cs0, /cs1 c in4 36 48 pf input capacitance ck0, /ck0, ck1, /ck1 c in5 30 38 pf input capacitance dm0 ~ dm7 c in6 10 18 pf data input / output capacitance dq0 ~ dq63, dqs0 ~ dqs7 c io1 10 18 pf
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 8 dc characteristics i (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v in = 0 to 3.6v, all other pins are not tested under v in =0v 2. d out is disabled, v out =0 to 2.7v parameter symbol min. max unit note input leakage current add, cmd, /cs, cke i li -32 32 ua 1 ck0, /ck0, ck1, /ck1 -16 16 output leakage current i lo -5 5 ua 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma output low voltage v ol -v tt - 0.76 v i ol = +15.2ma
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 9 dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) parameter symbol test condition speed unit note -d43 -d4 operating current idd0 one bank; active - precharge ; trc=trc(min); tck=tck(min) ; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1480 ma operating current i dd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 1880 ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) 160 ma idle standby current i dd2f /cs=high, all banks idle; tck=tck(min); cke=high; address and control inputs changing once per clock cycle. vin=vref for dq, dqs and dm 560 ma idle quiet standby current i dd2q /cs>=vih(min); all banks idle ; cke>=vih(min); addresses and other control inputs stable, vin=vref for dq, dqs and dm 520 ma active power down standby current i dd3p one bank active; power down mode; cke=low, tck=tck(min) 192 ma active standby current i dd3n /cs=high; cke=high; one bank; active-precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inpu ts changing once per clock cycle 680 ma operating current i dd4r burst=2; reads; continuous burst; one bank active; address and control inputs chan ging once per clock cycle; tck=tck(min); iout=0ma 2520 ma operating current i dd4w burst=2; writes; continuous burst; one bank active; address and control inputs chan ging once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle 2520 auto refresh current i dd5 trc=trfc(min) - 14*tck for ddr400 at 200mhz 2680 self refresh current i dd6 cke =< 0.2v; external clock on; tck=tck(min) normal 80 ma low power 40 ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition 4600 ma
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 10 ac characteristics (ac operating conditions unless otherwise noted) parameter symbol ddr400 (d43) ddr400 (d4) unit note min max min max row cycle time trc 55 - 60 - ns auto refresh row cycle time trfc 70 - 70 - ns row active time tras 40 70k 40 70k ns active to read with auto precharge delay trap trcd or trasmin - trcd or trasmin -ns16 row address to column address delay trcd 15 - 18 - ns row active to row active delay trrd 10 - 10 - ns column address to column address delay tccd 1 - 1 - ck row precharge time trp 15 - 18 - ns write recovery time twr 15 - 15 - ns internal write to read command delay twtr 2 - 2 - ck auto precharge write recovery + precharge time tdal (twr/tck) + (trp/tck) - (twr/tck) + (trp/tck) -ck15 system clock cycle time cl = 3 tck 5 10 5 10 ns clock high level width tch 0.45 0.55 0.45 0.55 ck clock low level width tcl 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew tac -0.7 0.7 -0.7 0.7 ns dqs-out edge to clock edge skew tdqsck -0.55 0.55 -0.55 0.55 ns dqs-out edge to data-out edge skew tdqsq - 0.4 - 0.4 ns data-out hold time from dqs tqh t hp -t qhs - t hp -t qhs -ns1,10 clock half period thp min (tcl,tch) - min (tcl,tch) -ns1,9 data hold skew factor tqhs - 0.5 - 0.5 ns 10 data-out high-impedance window from ck,/ck thz tac(max) tac(max) ns 17 data-out low-impedance window from ck, /ck tlz -0.7 0.7 -0.7 0.7 ns input setup time (fast slew rate) tis 0.6 - 0.6 - ns 2,3,5,6 input hold time (fast slew rate) tih 0.6 - 0.6 - ns input setup time (slow slew rate) t is 0.7-0.7-ns 2,4,5,6 input hold time (slow slew rate) t ih 0.7-0.7-ns
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 11 ac characteristics (ac operating conditions unless otherwise noted) - continued - note : 1. this calculation accounts for tdqsq(max), the pul se width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a12, ba0~ba1, cke, /cs, /ras, /cas, /we. 3. for command/address input slew rate >=1.0v/ns 4. for command/address input slew rate >=0.5v/ns and <1.0v/ns this derating table is used to increase tis/tih in case where the input slew-rate is below 0.5v/ns. input setup / hold 5. slew-rate derating table. 6. ck, /ck slew rates are >=1.0v/ns 7. these parameters quarantee device timing, but they are not necessarily tested on eac h device, and they may be quaranteed by design or tester correlation. parameter symbol ddr400 (d43) ddr400 (d4) unit note min max min max input pulse width t ipw 2.2 - 2.2 - ns 6 write dqs high level width t dqsh 0.35 - 0.35 - ck write dqs low level width t dqsl 0.35 - 0.35 - ck clock to first rising edge of dqs-in t dqss 0.72 1.28 0.72 1.28 ck dqs falling edge to ck setup time t dss 0.2 0.2 ck dqs falling edge hold time from ck t dsh 0.2 0.2 ck data-in setup time to dqs-in (dq & dm) t ds 0.4 - 0.4 - ns 6,7,11 , 12,13 data-in hold time to dqs-in (dq & dm) t dh 0.4 - 0.4 - ns dq & dm input pulse width t dipw 1.75 - 1.75 - ns 6 read dqs preamble time t rpre 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0 - 0 - ck write dqs preamble hold time t wpreh 0.25 - 0.25 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 2 - 2 - ck exit self refresh to any execute command t xsc 200 - 200 - ck 8 average periodic refresh interval t refi - 7.8 - 7.8 us input setup / hold slew-rate delta tis delta tih v/ns ps ps 0.5 0 0 0.4 +50 0 0.3 +100 0
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 12 8. data latched at both rising and falling edges of data strobes(ldqs/udqs) : dq, ldm/udm. 9. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to co mplete self refresh exit and lock the internal dll circuit of ddr sdram. 10. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the de vice (i.e. this value can be greater t han the minimum specification limits for tcl and tch). 11. thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width distortion of on-chip cl ock circuits, data pin to pin skew and output pattern effects and p -channel to n-channel variation of the output drivers. 12 . this derating table is used to increase tds/tdh in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 13. i/o setup/hold plateau derating. this derating table is used to increase tds/tdh in case where the input level is flat below vref +/-310mv for a duration of up to 2ns. 14. i/o setup/hold delta inverse slew rate derating. this derating table is used to increase tds/tdh in case where the dq and dqs slew rates differ. the delta inverse slew rate is calculated as (1/slewrate1)-(1/slewrate2). for example, if slew rate 1=0.5v/ns and slew rate2 = 0.4v/n then the delta inverse slew rate = -0.5ns/v. 15. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal transi tions through the dc region must be monotonic. 16. tdal = (tdpl / tck ) + (trp / tck ). for each of the terms above, if not already an integer, round to the next highest integer. tck is equal to t he actual system clock cycle time. example: for ddr266b at cl=2.5 and tck = 7.5 ns, tdal = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) round up each non-integer to the next highest integer: = (2) + (3), tdal = 5 clock 17. for the parts which do not has internal ras lock out circuit, active to read with auto precharge delay should be tras - bl/2 x tck. 18. thz and tlz transitions occur in the same access time windows as valid data trasitions. these parameters are not refer enced to a specific voltage level but specify when the device output is no longer drivi ng (hz), or begins driving (lz). input setup / hold slew-rate delta tds delta tdh v/ns ps ps 0.5 0 0 0.4 +75 +75 0.3 +150 +150 i/o input level delta tds delta tdh mv ps ps +280 +50 +50 (1/slewrate1)-(1/slewrate2) delta tds delta tdh ns/v ps ps 000 +/-0.25 +50 +50 +/- 0.5 +100 +100
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 13 simplified command truth table note : 1. ldm/udm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a 0 ~a 12 and ba 0 ~ba 1 used for mode registering duing extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+t rp ). 4. if a write with autoprecharge command is detected by memo ry compoment in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+t dpl +t rp ). last data-in to prechage delay(t dpl ) which is also called write recovery time (twr) is needed to guarantee that the last data has been completely written. 5. if a 10 /ap is high when row precharge command being issued, ba 0 /ba 1 are ignored and all banks are selected to be precharged. command cken-1 cken /cs /ras /cas /we addr a10/ ap ba note extended mode register set h x llll op code 1,2 mode register set h x llll op code 1,2 device deselect hx hxxx x1 no operation lhhh bank active h x l l h h ra v 1 read h x lhlhca l v 1 read with autoprecharge h1,3 write hxlhllca l v 1 write with autoprecharge h1,4 precharge all banks hxllhlx hx1,5 precharge selected bank lv1 read burst stop h x l h h l x 1 auto refresh h h l l l h x 1 self refresh entryh l lllh x 1 exit l h hxxx 1 lhhh precharge power down mode entry h l hxxx x 1 lhhh 1 exit l h hxxx 1 lhhh 1 active power down mode (clock suspend) entry h l hxxx x 1 lvvv 1 exit l h x 1 ( h=logic high level, l=logic low level, x= don?t care, v=valid data input, op code=operand code, nop=no operation )
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 14 package dimensions front 31.75 mm 20.00 mm 1 39 41 199 2.00 mm component keepout area 2.00 mm back side 67.60 mm 3.8mm max. 1.1mm max.
rev. 0.2 / apr. 2004 15 serial presence detect spd specification (128mx 64 unbuffered ddr so-dimm)
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 16 serial presence detect byte# function description function supported hexa value note d43 d4 d43 d4 0 number of bytes written into serial memory at module manufacturer 128 bytes 128 bytes 80h 80h 1 total number of bytes in spd device 256 bytes 256 bytes 08h 08h 2 fundamental memory type ddr sdram ddr sdram 07h 07h 3 number of row address on this assembly 13 13 0dh 0dh 1 4 number of column address on this assembly 11 11 0bh 0bh 1 5 number of physical banks on dimm 2bank 2bank 02h 02h 6 module data width 64 bits 64 bits 40h 40h 7 module data width (continued) - - 00h 00h 8 module voltage interface levels(vddq) sstl 2.5v sstl 2.5v 04h 04h 9 ddr sdram cycle time at cas latency=x (tck) 5.0ns 5.0ns 50h 50h 2 10 ddr sdram access time from clock at cl=x (tac) +/-0.7ns +/-0.7ns 70h 70h 2 11 module configuration type none none 00h 00h 12 refresh rate and type 7.8us & self refresh 7.8us & self refresh 82h 82h 13 primary ddr sdram width x8 x8 08h 08h 14 error checking ddr sdram data width n/a n/a 00h 00h 15 minimum clock delay for back-to-back random column address(tccd) 1 clk 1 clk 01h 01h 16 burst lengths supported 2,4,8 2,4,8 0eh 0eh 17 number of banks on each ddr sdram 4 banks 4 banks 04h 04h 18 cas latency supported 2, 2.5, 3 2, 2.5, 3 1ch 1ch 19 cs latency 0 0 01h 01h 20 we latency 1 1 02h 02h 21 ddr sdram module attributes differentia l clock input differential clock input 20h 20h 22 ddr sdram device attributes : general +/-0.2voltage toler- ance, concurrent auto pre- charge tras lock out +/-0.2voltage toler- ance, concurrent auto pre- charge tras lock out c0h c0h 23 ddr sdram cycle time at cl=x-0.5(tck) 6.0ns 6.0ns 60h 60h 2 24 ddr sdram access time from clock at cl=x-0.5(tac) +/-0.7ns +/-0.7ns 70h 70h 2 25 ddr sdram cycle time at cl=x-1(tck) 7.5ns 7.5ns 75h 75h 2 26 ddr sdram access time from clock at cl=x-1(tac) +/-0.75ns +/-0.75ns 75h 75h 2 27 minimum row precharge time(trp) 15ns 18ns 3ch 48h 28 minimum row activate to row active delay(trrd) 10ns 10ns 28h 28h 29 minimum ras to cas delay(trcd) 15ns 18ns 3ch 48h 30 minimum active to precharge time(tras) 40ns 40ns 28h 28h 31 module row density 512mb 512mb 80h 80h 32 command and address signal input setup time(tis) 0.60ns 0.60ns 60h 60h 33 command and address signal input hold time(tih) 0.60ns 0.60ns 60h 60h 34 data signal input setup time(tds) 0.40ns 0.40ns 40h 40h 35 data signal input hold time(tdh) 0.40ns 0.40ns 40h 40h 36~40 reserved for vcsdram undefined undefined 00h 00h 41 minimum active / auto-refresh time ( trc) 55ns 58ns 37h 3ah 42 minimum auto-refresh to active/auto-refresh command period(trfc) 70ns 70ns 46h 46h 43 maximum cycle time (tck max) 10ns 10ns 28h 28h 44 maximim dqs-dq skew time(tdqsq) 0.4ns 0.4ns 28h 28h 45 maximum read data hold skew factor(tqhs) 0.5ns 0.5ns 50h 50h 46~61 superset information(may be used in future) undefined undefined 00h 00h 62 spd revision code initial release initial release 00h 00h 63 checksum for bytes 0~62 - - a8h c3h bin sort :d43(ddr400 3-3-3) / d4(ddr400 3-4-4)
hymd512m646b(l)f8-d43/d4 rev. 0.2 / apr. 2004 17 serial presence detect - continued - note : 1. the bank address is excluded 2. these value is based on the component specification 3. these bytes are programmed by code of date week & date year 4. these bytes apply to hynix?s own module serial number system 5. these bytes undefined and coded as ?00h? 6. refer to hynix web site byte 85~87, low power part byte# function description function supported hexa value note d43 d4 d43 d4 64 manufacturer jedec id code hynix jedec id hynix jedec id adh adh 65~71 --------- manufacturer jedec id code - - 00h 00h 72 manufacturing location hynix(korea area) hsa(united states area) hse(europe area) hsj(japan area) singapore asia area hynix(korea area) hsa(united states area) hse(europe area) hsj(japan area) singapore asia area 0*h 1*h 2*h 3*h 4*h 5*h 0*h 1*h 2*h 3*h 4*h 5*h 6 73 manufacture part number(hynix memory module) h h 48h 48h 74 -------- manufacture part number(hynix memory module) y y 59h 59h 75 -------- manufacture part number(hynix memory module) m m 4dh 4dh 76 manufacture part number (ddr sdram) d d 44h 44h 77 manufacture part number(memory density) 5 5 35h 35h 78 manufacture part number(module depth) 1 1 31h 31h 79 ------- manufacture part number(module depth) 2 2 32h 32h 80 manufacture part number(module type) m m 4dh 4dh 81 manufacture part number(data width) 6 6 36h 36h 82 -------manufacture part number(data width) 4 4 34h 34h 83 manufacture part number(refresh, # of bank.) 6(8k refresh,4bank) 6(8k refresh,4bank) 36h 36h 84 manufacture part number(component generation) b b 42h 42h 85 manufacture part number(component module type) f f 46h 46h 86 manufacture part number(component generation) 8 8 38h 38h 87 manufacture part number(hyphen) ?-? ?-? 2dh 2dh 88 manufacture part number(minimum cycle time) d d 44h 44h 89 manufacture part number(minimum cycle time) 4 4 34h 34h 90 manufacture revision code(minimum cycle time) 3 - 33h - 91 manufacture revision code(for component) 92 manufacture revision code (for pcb) 93 manufacturing date(year) 3 94 manufacturing date(week) 3 95~98 module serial number 4 99~127 manufacturer specific data (may be used in future) undefined undefined 00h 00h 5 128~255 open for customer use undefined undefined 00h 00h 5 byte # function description function supported hexa value note d43 d4 d43 d4 85 manufacture part number(low power part) l 4ch 86 manufacture part number(component configuration) f 46h 87 manufacture part number(hyphen) 8 38h

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